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ASAHI KASEI
[AK4124]
AK4124
192kHz / 24Bit High Performance Asynchronous SRC
GENERAL DESCRIPTION AK4124 is a stereo digital sample rate converter (SRC). The input sample rate ranges from 8kHz to 216kHz. The output sample rate is from 8kHz to 216kHz. By using the AK4124, the system can take very simple configuration because the AK4124 has an internal PLL and does not need any master clock at slave mode. Then the AK4124 is suitable for the application interfacing to different sample rates like high-end Car Audio, DVD recorder, etc.
FEATURES 1. SRC * Asynchronous Sample Rate Converter * Input Sample Rate Range (fsi) : 8kHz 216kHz * Output Sample Rate (fso) : 8kHz 216kHz * Input to Output Sample Rate Ratio : 1/6 to 6 * THD+N : -130dB * Dynamic Range : 140dB (A-weighted) * I/F format : MSB justified, LSB justified and I2S compatible * PLL for Internal Operation Clock * Clock for Master mode : 128/192/256/384/512/768fsi, 128/192/256/384/512/768fso * SRC Bypass mode * Soft Mute Function 2. Power Supply * AVDD, DVDD: 3.0 3.6V (typ. 3.3V) 3. Ta = -40 85C 4. Package : 30pin VSOP
IDIF2 IDIF1 IDIF0 AVDD AVSS DVDD DVSS ODIF1 ODIF0 OBIT1 OBIT0 IBICK ILRCK SDTI Serial Audio I/F Serial Audio I/F OLRCK OBICK SDTO OMCLK PDN PLL2 PLL1 PLL0 SMUTE PLL DITHER
SRC
UNLOCK
IMCLK
CMODE2 CMODE1 CMODE0
MS0288-E-01 -1-
2004/08
ASAHI KASEI
[AK4124]
Ordering Guide
AK4124VF AKD4124 -40 +85C 30pin VSOP (0.65mm pitch) Evaluation Board for AK4124
Pin Layout
FILT AVSS PDN SMUTE DITHER PLL2 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 PLL0 PLL1 UNLOCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Top View
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AVDD DVSS DVDD OMCLK OLRCK OBICK SDTO ODIF1 ODIF0 CMODE2 CMODE1 CMODE0 IMCLK OBIT1 OBIT0
MS0288-E-01 -2-
2004/08
ASAHI KASEI
[AK4124]
Compatibility with AK4121
AK4124 DITHER PLL2 -130dB 140dB -0.01dB (typ) 8kHz 216kHz Yes 128/192/256/384/512/768fsi 128/192/256/384/512/768fso 16/18/20/24 bit No Yes No 30VSOP AK4121 DEM0 DEM1 -113dB 117dB -0.2dB (typ) 8kHz 96kHz No No 256/384/512/768fso 16/20 bit Yes (32k/44.1k/48kHz) No Yes (TVDD) 24VSOP
Pin 5 Pin 6 THD+N D-Range (A-weighted) Gain between Input and Output Signal fs Master mode for Input PORT MCLK for Master mode (Input PORT) MCLK for Master mode (Output PORT) Output Data Length De-emphasis Filter PLL Unlock Flag (UNLOCK pin) 5V tolerant Package
MS0288-E-01 -3-
2004/08
ASAHI KASEI
[AK4124]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Name FILT AVSS PDN SMUTE DITHER PLL2 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 PLL0 PLL1 UNLOCK OBIT0 OBIT1 IMCLK CMODE0 CMODE1 CMODE2 ODIF0 ODIF1 SDTO OBICK OLRCK OMCLK DVDD DVSS AVDD I/O O I I I I I/O I/O I I I I I I O I I I I I I I I O I/O I/O I Function PLL Loop Filter Pin Analog Ground Pin Power-Down Mode Pin "H": Power up, "L": Power down reset and initializes the control register. Soft Mute Pin "H" : Soft Mute, "L" : Normal Operation Dither Enable Pin "H" : Dither ON, "L" : Dither OFF PLL Mode Select 2 Pin Input Channel Clock Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin Audio Interface Format 0 Pin for Input PORT Audio Interface Format 1 Pin for Input PORT Audio Interface Format 2 Pin for Input PORT PLL Mode Select 0 Pin PLL Mode Select 1 Pin Unlock Status Pin Bit Length Select 0 Pin for Output Data Bit Length Select 1 Pin for Output Data Master Clock Input Pin for Input PORT Clock Mode Select 0 Pin Clock Mode Select 1 Pin Clock Mode Select 2 Pin Audio Interface Format 0 Pin for Output PORT Audio Interface Format 1 Pin for Output PORT Audio Serial Data Output Pin for Output PORT Audio Serial Data Clock Pin for Output PORT Output Channel Clock Pin for Output PORT Master Clock Input Pin for Output PORT Digital Power Supply Pin, 3.0 3.6V Digital Ground Pin Analog Power Supply Pin, 3.0 3.6V
Note: All input pins should not be left floating.
MS0288-E-01 -4-
2004/08
ASAHI KASEI
[AK4124]
Handling of Unused pins
The unused digital I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name FILT SMUTE, DITHER IMCLK, OMCLK UNLOCK Setting This pin should be open. These pins should be connected to DVSS. These pins should be connected to DVSS in slave mode. This pin should be open.
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1) Parameter Power Supplies: Analog Digital |AVSS - DVSS| (Note 2) Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Temperature (Power applied) Storage Temperature Symbol AVDD DVDD GND IIN VIND Ta Tstg min -0.3 -0.3 -0.3 -40 -65 max 4.6 4.6 0.3 10 DVDD+0.3 85 150 Units V V V mA V C C
Note 1. All voltages with respect to ground. Note 2. AVSS, BVSS and DVSS must be connected to the same ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 1) Parameter Symbol min typ Power Supplies Analog AVDD 3.0 3.3 (Note 3) Digital DVDD 3.0 3.3
Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD and DVDD is not critical.
max 3.6 AVDD
Units V V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0288-E-01 -5-
2004/08
ASAHI KASEI
[AK4124]
SRC CHARACTERISTICS (Ta=25C; AVDD=DVDD=3.3V; AVSS=DVSS=0V; data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter Symbol min typ max Units SRC Characteristics: Resolution 24 Bits Input Sample Rate FSI 8 216 kHz Output Sample Rate FSO 8 216 kHz THD+N (Input = 1kHz, 0dBFS, Note 4) FSO/FSI = 44.1kHz/48kHz -130 dB FSO/FSI = 48kHz/44.1kHz -124 dB FSO/FSI = 48kHz/192kHz -129 dB FSO/FSI = 192kHz/48kHz -124 dB Worst Case (FSO/FSI = 48kHz/8kHz) -108 dB Dynamic Range (Input = 1kHz, -60dBFS, Note 4) FSO/FSI = 44.1kHz/48kHz 136 dB FSO/FSI = 48kHz/44.1kHz 136 dB FSO/FSI = 48kHz/192kHz 136 dB FSO/FSI = 192kHz/48kHz 132 dB Worst Case (FSO/FSI = 48kHz/32kHz) 132 dB Dynamic Range (Input = 1kHz, -60dBFS, A-weighted, Note 4) FSO/FSI = 44.1kHz/48kHz 140 dB Ratio between Input and Output Sample Rate FSO/FSI 1/6 6 Note 4. Measured by Audio Precision System Two Cascade.
MS0288-E-01 -6-
2004/08
ASAHI KASEI
[AK4124]
FILTER CHARACTERISTICS (Ta=25C; AVDD, DVDD=3.0 3.6V) Parameter Symbol min Digital Filter Passband -0.001dB 0.985 FSO/FSI 6.000 PB 0 0.905 FSO/FSI < 0.985 PB 0 0.714 FSO/FSI < 0.905 PB 0 0.656 FSO/FSI < 0.714 PB 0 0.536 FSO/FSI < 0.656 PB 0 0.492 FSO/FSI < 0.536 PB 0 0.452 FSO/FSI < 0.492 PB 0 0.357 FSO/FSI < 0.452 PB 0 0.324 FSO/FSI < 0.357 PB 0 0.246 FSO/FSI < 0.324 PB 0 0.226 FSO/FSI < 0.246 PB 0 0.1667 FSO/FSI < 0.226 PB 0 Stopband 0.985 FSO/FSI 6.000 SB 0.5417FSI 0.905 FSO/FSI < 0.985 SB 0.5021FSI 0.714 FSO/FSI < 0.905 SB 0.3965FSI 0.656 FSO/FSI < 0.714 SB 0.3643FSI 0.536 FSO/FSI < 0.656 SB 0.2974FSI 0.492 FSO/FSI < 0.536 SB 0.2732FSI 0.452 FSO/FSI < 0.492 SB 0.2510FSI 0.357 FSO/FSI < 0.452 SB 0.1983FSI 0.324 FSO/FSI < 0.357 SB 0.1822FSI 0.246 FSO/FSI < 0.324 SB 0.1366FSI 0.226 FSO/FSI < 0.246 SB 0.1255FSI 0.1667 FSO/FSI < 0.226 SB 0.0911FSI Passband Ripple PR Stopband Attenuation SA 113 Group Delay (Note 5) GD -
typ
max 0.4583FSI 0.4167FSI 0.3195FSI 0.2852FSI 0.2182FSI 0.1982FSI 0.1740FSI 0.1212FSI 0.1072FSI 0.0595FSI 0.0484FSI 0.0182FSI
Units kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz dB dB 1/fs
0.01 56 -
Note 5. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output, when LRCK for Output data corresponds with LRCK for Input.
DC CHARACTERISTICS (Ta=25C; AVDD, DVDD=3.0 3.6V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL High-Level Output Voltage (Iout=-400A) VOH DVDD-0.4 Low-Level Output Voltage (Iout=400A) VOL Input Leakage Current Iin Power Supplies Power Supply Current Normal operation (PDN pin = "H") FSI=FSO=48kHz at Slave Mode: AVDD=DVDD=3.3V FSI=FSO=192kHz at Master Mode: AVDD=DVDD=3.3V : AVDD=DVDD=3.6V Power down (PDN pin = "L") (Note 6) AVDD+DVDD Note 6. All digital input pins are held DVSS.
typ -
max 30%DVDD 0.4 10
Units V V V V A
13 55 85 10 100
mA mA mA A
MS0288-E-01 -7-
2004/08
ASAHI KASEI
[AK4124]
SWITCHING CHARACTERISTICS (Ta=25C; AVDD, DVDD=3.0 3.6V; CL=20pF) Parameter Symbol min Master Clock Timing Frequency fCLK 1.024 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK for Input data (ILRCK) Frequency fs 8 Duty Cycle Duty 48 LRCK for Output data (OLRCK) Frequency fs 8 Duty Cycle Slave Mode Duty 48 Master Mode Duty
Audio Interface Timing Input PORT (Slave mode) IBICK Period (8kHz 108kHz) (108kHz 216kHz) IBICK Pulse Width Low Pulse Width High ILRCK Edge to IBICK "" (Note 7) IBICK "" to ILRCK Edge (Note 7) SDTI Hold Time from IBICK "" SDTI Setup Time to IBICK "" Input PORT (Master mode) IBICK Frequency IBICK Duty IBICK "" to ILRCK SDTI Hold Time from IBICK "" SDTI Setup Time to IBICK "" Output PORT (Slave mode) OBICK Period (8kHz 108kHz) (108kHz 216kHz) OBICK Pulse Width Low Pulse Width High OLRCK Edge to OBICK "" (Note 7) OBICK "" to OLRCK Edge (Note 7) 2 OLRCK to SDTO (MSB) (Except I S mode) OBICK "" to SDTO Output PORT (Master mode) OBICK Frequency OBICK Duty OBICK "" to OLRCK OBICK "" to SDTO Reset Timing PDN Pulse Width (Note 8)
typ
max 41.472
Units MHz ns ns kHz % kHz % %
50
216 52 216 52
50 50
tBCK tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS fBCK dBCK tMBLR tSDH tSDS tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD fBCK dBCK tMBLR tBSD tPD
1/128fs 1/64fs 27 27 15 15 15 15 64fs 50 -20 15 15 1/128fs 1/64fs 27 27 20 20 20
ns ns ns ns ns ns ns ns Hz % ns ns ns ns ns ns ns ns ns ns ns Hz % ns ns ns
20 20
64fs 50 -20 -20 150 20 20
Note 7. BICK rising edge must not occur at the same time as LRCK edge. Note 8. The AK4124 can be reset by bringing the PDN pin = "L".
MS0288-E-01 -8-
2004/08
ASAHI KASEI
[AK4124]
Timing Diagram
1/fCLK VIH MCLK VIL tCLKH 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL
Clock Timing
VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD
tCLKL
SDTO tSDS tSDH
50%DVDD
VIH SDTI VIL
Audio Interface Timing (Slave mode) Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK.
MS0288-E-01 -9-
2004/08
ASAHI KASEI
[AK4124]
LRCK
50%DVDD
tMBLR
dBCK 50%DVDD
BICK
tBSD
SDTO tSDS tSDH
50%DVDD
VIH SDTI VIL
Audio Interface Timing (Master mode)
Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK.
tPD PDN VIL
Power Down & Reset Timing
MS0288-E-01 - 10 -
2004/08
ASAHI KASEI
[AK4124]
OPERATION OVERVIEW System Clock & Audio Interface Format for Input PORT
The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK (Mode 0 2 of Table 2) or IBICK (Mode 4 7 of Table 2) in slave mode. The MCLK is not needed in slave mode. And an internal system clock is created by IMCLK (Mode 8 15 of Table 2) in master mode. The PLL2-0 pins and IDIF2-0 pins select the master/slave and PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when PDN pin = "L". The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2's compliment format. The SDTI is latched on the rising edge of IBICK. Select the audio interface format when PDN pin = "L". When in BYPASS mode, both IBICK and OBICK are fixed to 64fs. Mode 0 1 2 3 4 5 6 7 IDIF2 L L L L H H H H IDIF1 L L H H L L H H IDIF0 SDTI Format ILRCK IBICK IBICK Freq L 16bit, LSB justified 32fsi H 20bit, LSB justified 40fsi Input Input L 24/20bit, MSB justified 48fsi H 24/16bit, I2S Compatible 48fsi or 32fsi L 24bit, LSB justified 48fsi H 24bit, MSB justified 64fs Output Output L 24bit, I2S Compatible 64fs H Reserved Table 1. Input Audio Interface Format (Input PORT) PLL2 L L Slave IMCLK = DVSS IBICK = Input ILRCK = Input L L H H H H L L L L H H H H PLL1 L L H PLL0 L H L ILRCK Freq 8k 96kHz 8k 216kHz 16k 216kHz (Note 1) IBICK Freq Depending on IDIF2-0 Master / Slave
Slave
Master
Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Master / Slave
IMCLK Not needed. (Note 4)
SMUTE (Note 5) Manual Semi-Auto
Master IMCLK = Input IBICK = Output ILRCK = Output
H H Reserved L L 32fsi (Note 3) Not L H 64fsi 8k 216kHz needed. (Note 2) H L 128fsi (Note 4) 64fsi H H L L 128fs 8k 216kHz L H 256fs 8k 108kHz H L 512fs 8k 54kHz H H 128fs 8k 216kHz 64fs L L 192fs 8k 216kHz L H 384fs 8k 108kHz H L 768fs 8k 54kHz H H 192fs 8k 216kHz Table 2. PLL Setting (Input PORT)
Manual Semi-Auto Manual Semi-Auto Manual Semi-Auto
Note 1. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to "PLL Loop Filter". Note 2. The IBCIK must be continuous except when the clocks are changed. Note 3. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible. Note 4. Fixed to DVSS. Note 5. Refer to "Soft Mute Operation" for Manual mode and Semi-Auto mode.
MS0288-E-01 - 11 -
2004/08
ASAHI KASEI
[AK4124]
ILRCK
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
IBICK(32fs) SDTI(i) IBICK(64fs) SDTI(i)
Don't Care 15:MSB, 0:LSB Lch Data Rch Data 15 14 13 12 10 Don't Care 15 14 13 12 210 15 14 13 0123 7 6 5 4 3 2 1 0 15 14 13 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1
Figure 1. Mode 0 Timing
ILRCK
012 12 13 24 31 0 1 2 12 13 24 31 0 1
IBICK(64fs) SDTI(i)
Don't Care 19:MSB, 0:LSB Lch Data Rch Data 19 8 10 Don't Care 19 8 10
Figure 2. Mode 1 Timing
ILRCK
012 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1
IBICK(64fs) SDTI(i)
23 22 43210 Don't Care 23 22 43210 Don't Care 23
23:MSB, 0:LSB Lch Data Rch Data
Figure 3. Mode 2,5 Timing (24bit MSB)
ILRCK
0123 21 22 23 24 25 012 21 22 23 24 25 01
IBICK(64fs) SDTI(i)
23 22 4 3 2 1 0 Don't Care 23 22 43210 Don't Care
23:MSB, 0:LSB Lch Data Rch Data
2
Figure 4. Mode 3, 6 Timing (24bit I S)
MS0288-E-01 - 12 -
2004/08
ASAHI KASEI
[AK4124]
ILRCK
012 89 24 31 0 1 2 89 24 31 0 1
IBICK(64fs) SDTI(i)
Don't Care 23:MSB, 0:LSB Lch Data Rch Data 23 8 10 Don't Care 23 8 10
Figure 5. Mode 4 Timing
System Clock & Audio Interface Format for Output PORT
The output port works in master mode or slave mode. The MCLK is not needed in slave mode. The CMODE2-0 pins select the master/slave and bypass mode. The CMODE2-0 pins should be controlled when PDN pin = "L". The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio data is MSB first, 2's compliment format. The SDTO is clocked out on the falling edge of OBICK. Select the audio interface format when PDN pin = "L". When in BYPASS mode, both IBICK and OBICK are fixed to 64fs. Mode 0 1 2 3 4 5 6 7 CMODE 2 L L L L H H H H CMODE CMODE0 Master / Slave OMCLK 1 L L Master 256fso L H Master 384fso H L Master 512fso H H Master 768fso L L Slave Not used. Set to DVSS. L H Master 128fso H L Master 192fso H H Master (Bypass) Not used. Set to DVSS. Table 3. Master/Slave Control (Output PORT) Mode ODIF1 ODIF0 SDTO Format 0 L L LSB justified 1 L H (Reserved) 2 H L MSB justified 3 H H I2S Compatible Table 4. Output Audio Interface Format 1 (Output PORT) Mode 0 1 2 3 4 5 6 7 Master / Slave Slave CMODE2-0 = "HLL" Master Except CMODE2-0 = "HLL" OBIT1 OBIT0 SDTO OLRCK OBICK OBICK Frequency MSB justified, I2S LSB justified 32fso 36fso 64fso 40fso 48fso 64fso fso 8k 108kHz 8k 108kHz 8k 54kHz 8k 54kHz 8k 216kHz 8k 216kHz 8k 216kHz 8k 216kHz
L L 16bit L H 18bit Input Input H L 20bit H H 24bit L L 16bit L H 18bit Output Output H L 20bit H H 24bit Table 5. Output Audio Interface Format 2 (Output PORT)
MS0288-E-01 - 13 -
2004/08
ASAHI KASEI
[AK4124]
OLRCK
01 8 9 10 11 12 13 14 15 16 17 20 21 22 23 29 30 31 0 1 8 9 10 11 12 13 14 15 16 17 20 21 22 23 29 30 31 0 1 2
OBICK(64fs) SDTO(O)
15:MSB, 0:LSB 15 14 11 10 9 8 210 15 14 11 10 9 8 210
SDTO(O)
17:MSB, 0:LSB
17 16 15 14
11 10 9 8
210
17 16 15 14
11 10 9 8
210
SDTO(O) SDTO(O)
19 18 17 16 15 14 19:MSB, 0:LSB 23 22 21 20 19 18 17 16 15 14 23:MSB, 0:LSB Lch Data
11 10 9 8
210
19 18 17 16 15 14
11 10 9 8
210
11 10 9 8
210
23 22 21 20 19 18 17 16 15 14
11 10 9 8
210
Rch Data
Figure 6. LSB Timing
OLRCK
01234 13 14 15 16 17 18 19 20 21 22 23 24 31 0 1 2 3 4 13 14 15 16 17 18 19 20 21 22 23 24 31 0 1 2
OBICK(64fs) SDTO(O) SDTO(O) SDTO(O) SDTO(O)
15 14 13 12 210 15:MSB, 0:LSB 17 16 15 14 43210 17:MSB, 0:LSB 19 18 17 16 6543210 19:MSB, 0:LSB 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0 23:MSB, 0:LSB Lch Data Rch Data 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0 23 22 19 18 17 16 6543210 19 18 17 16 15 14 43210 17 16 15 14 13 12 210 15 14
Figure 7. MSB Timing
OLRCK
01234 14 15 16 17 18 19 20 21 22 23 24 01234 14 15 16 17 18 19 20 21 22 23 24 31 0 1 2
OBICK(64fs) SDTO(O) SDTO(O) SDTO(O) SDTO(O)
15 14 13 12 210 15:MSB, 0:LSB 17 16 15 14 43210 17:MSB, 0:LSB 19 18 17 16 6543210 19:MSB, 0:LSB 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0 23:MSB, 0:LSB Lch Data Rch Data
2
15 14 13 12
210
15
17 16 15 14
43210
17
19 18 17 16
6543210
19
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23
Figure 8. I S Compatible Timing
MS0288-E-01 - 14 -
2004/08
ASAHI KASEI
[AK4124]
Soft Mute Operation
1. Manual mode Soft mute operation is performed in the digital domain of the SRC output. Soft mute can be controlled by SMUTE pin. When SMUTE pin goes "H", the SRC output data is attenuated by - within 1024 OLRCK cycles. When the SMUTE pin goes "L" the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 OLRCK cycles. If the soft mute is cancelled before mute state after starting of the operation, the attenuation is discontinued and returned to 0dB by the same cycles. The soft mute is effective for changing the signal source.
SM U T E 1024/fso 0dB Attenuation (1) (3)
-
GD (2) SD T O GD
Figure 9. Soft Mute Function (Manual Mode) (1) The output data is attenuated by - during 1024 OLRCK cycles (1024/fso). (2) Digital output delay from the digital input is called the group delay (GD). (3) If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to 0dB by the same number of clock cycles. 2. Semi-Auto mode The soft mute is cancelled automatically by the setting of PLL2-0 pins (refer to Table 2), after the AK4124 detects the rising edge (PDN pin = "L" "H") and the mute is continued during 4410/fso=100ms@fso=44.1kHz. After PDN pin = "L" "H" and when SMUTE pin is "H", the mute is not cancelled.
PD N pin
"L"
SM U T E pin
D on't care
"L"
0dB Attenuation 4410/fso
(1)
-
(2) GD
SD T O
Figure 10. Soft Mute Function (Semi-Auto Mode) (1) The output data is attenuated by - during 1024 OLRCK cycles (1024/fso). (2) Digital output delay from the digital input is called the group delay (GD).
MS0288-E-01 - 15 -
2004/08
ASAHI KASEI
[AK4124]
Dither
The AK4124 has the dither circuit. The dither circuit adds the dither to the LSB of the output data set with the OBIT1-0 pins by DITHER pin = "H" regardless of the SRC mode or the SRC bypass mode.
System Reset
Bringing the PDN pin = "L" sets the AK4124 power-down mode and initializes the digital filter. The AK4124 should be reset once by bringing PDN pin = "L" upon power-up. When PDN pin = "L", the SDTO output is "L". The SDTO valid time is 100ms. Until then, the SDTO outputs "L".
Case 1
External clocks (Input port) SDTI External clocks (Output port) PDN
< 100ms
Don't care Don't care Don't care
Input Clocks 1 Input Data 1 Output Clocks 1
Input Clocks 2 Input Data 2 Output Clocks 2
Don't care Don't care Don't care
< 100ms
Normal operation PD PLL lock & fs detection Normal operation
(Internal state) Power-down SDTO
PLL lock & fs detection
Power-down
"0" data
Normal data
"0" data
Normal data
"0" data
UNLOCK
Figure 11. System Reset
Case 2
External clocks (Input port) SDTI External clocks (Output port) PDN
< 100ms PLL lock & fs detection Normal operation
(No Clock) (Don't care) (Don't care)
Input Clocks Input Data Output Clocks
Don't care Don't care Don't care
(Internal state) Power-down
PLL Unlock
Power-down
SDTO
"0" data
Normal data
"0" data
UNLOCK
Figure 12. System Reset 2
MS0288-E-01 - 16 -
2004/08
ASAHI KASEI
[AK4124]
Internal Reset Function for Clock Change
The change of the clock supplied to AK4124 is shown in Figure 13. When the frequency transition occurs gradually without phase change or the clock of output port is changed keeping fso/fsi > 4, the internal reset is not executed and the SDTO takes time over 100ms to output normal data. To output normal data within 100ms, please reset by PDN pin = "L".
External clocks (Input port or Output port) PDN pin
< 100ms
Clocks 1
Don't care
Clocks 2
(Internal state) Normal operation Power-down PLL lock &
Note1
fs detection
Normal operation
SDTO SMUTE (Note2, recommended) Att.Level 0dB -dB
Normal data
Normal data 1024/fso
1024/fso
Figure 13. Sequence of changing clocks
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to "0" from GD before PDN pin goes "L", which will cause the data on SDTO to remain "0". Note 2. SMUTE can also be used to remove the unknown data.
UNLOCK pin
The UNLOCK pin outputs "L" when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin outputs "H". When PDN pin = "L", the UNLOCK pin outputs "H".
MS0288-E-01 - 17 -
2004/08
ASAHI KASEI
[AK4124]
PLL Loop Filter
The C1 and R should be connected in series and attached between FILT pin and AVSS in parallel with C2. Please be careful the noise onto the FILT pin. When using IBICK, the value of an external element doesn't depend on the IBICK input frequency.
AK4124
FILT R C1 AVSS
C2
Figure 14. PLL Loop Filter [Input PORT in slave mode] 1. When using ILRCK PLL2 L L L PLL1 L L H PLL0 L ILRCK R [] 8k 96kHz 1.8k 5% 8k 216kHz 1k 5% H 16k 216kHz 1.5k 5% 8k 216kHz 1k 5% L 16k 216kHz 1.5k 5% Table 6. PLL Loop Filter (ILRCK Mode) C1 [F] 0.68 30% 1.0 30% 0.68 30% 1.0 30% 0.68 30% C2 [nF] 0.68 30% 2.2 30% 0.68 30% 2.2 30% 0.68 30%
- Note. The mode of between 16kHz and 216kHz the capacitor value (C1, C2) can be small. 2. When using IBICK PLL2 H PLL1 * PLL0 ILRCK R [] C1 [F] * 8k 216kHz 470 5% 0.22 30% Table 7. PLL Loop Filter (IBICK Mode, *: Don't care) C2 [nF] 1.0 30%
Note. The IBCIK must be continuous except when the clocks are changed. Note. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible. [Input PORT in master mode] 1. When IMCLK is 256fs, 384fs, 512fs or 768fs, an external element is not needed. 2. When IMCLK is 128fs or 192fs in master mode, an external element is needed in case of using IBICK.
MS0288-E-01 - 18 -
2004/08
ASAHI KASEI
[AK4124]
SYSTEM DESIGN
Figure 15 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. * Input PORT : Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified * Output PORT : Slave mode, 24bit MSB justified * Dither = OFF
470 1.0n 1 FILT 0.22 2 AVSS Reset 3 PDN 4 SMUTE 5 DITHER 6 PLL2 fsi 64fsi 7 ILRCK 8 IBICK 9 SDTI 10 IDIF0 11 IDIF1 12 IDIF2 13 PLL0 14 PLL1 15 UNLOCK DVSS 29 DVDD 28 OMCLK 27 OLRCK 26 OBICK 25 0.1 AVDD 30 0.1
10
Supply 3.0 ~ 3.6V
fso 64fso DSP
AK4124
SDTO 24 ODIF1 23 ODIF0 22 CMODE2 21 CMODE1 20 CMODE0 19 IMCLK 18 OBIT1 17 OBIT0 16
DSP, uP
Note: - AVSS and DVSS of the AK4124 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All digital input pins should not be left floating. Figure 15. Typical Connection Diagram (Slave mode)
MS0288-E-01 - 19 -
2004/08
ASAHI KASEI
[AK4124]
* Input PORT : Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified * Output PORT : Master mode, 24bit MSB justified * Dither = OFF
470 1.0n 1 FILT 0.22 2 AVSS Reset 3 PDN 4 SMUTE 5 DITHER 6 PLL2 fsi 64fsi 7 ILRCK 8 IBICK 9 SDTI DSP, uP 10 IDIF0 11 IDIF1 12 IDIF2 13 PLL0 14 PLL1 15 UNLOCK CMODE2 21 CMODE1 20 CMODE0 19 IMCLK 18 OBIT1 17 OBIT0 16 DVSS 29 DVDD 28 OMCLK 27 OLRCK 26 OBICK 25 0.1 AVDD 30 0.1
10
Supply 3.0 ~ 3.6V
128fso fso 64fso DSP
AK4124
SDTO 24 ODIF1 23 ODIF0 22
Note: - AVSS and DVSS of the AK4124 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All digital input pins should not be left floating. Figure 16. Typical Connection Diagram (Master mode)
1. Grounding and Power Supply Decoupling
The AK4124 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. Decoupling capacitors should be as near to the AK4124 as possible, with the small value ceramic capacitor being the nearest.
MS0288-E-01 - 20 -
2004/08
ASAHI KASEI
[AK4124]
2. Jitter Tolerance
Figure 17 shows the jitter tolerance to ILRCK and IBICK for AK4124. The jitter frequency and the jitter amplitude shown in Figure 17 define the jitter quantity. When the jitter amplitude is 0.01Uipp or less, the AK4124 operate normally regardless of the jitter frequency.
AK4124 Jitter Tolerance
10.00
1.00 Amplitude [UIpp]
(3)
0.10
(2)
0.01
(1)
0.00 1 10 100 Jitter Frequency [Hz] 1000 10000
(1) Normal operation (2) There is a possibility that the distortion degrades. (It may degrade up to about -50dB.) (3) There is a possibility that the output data is lost. Note: - When PLL2-0 = "L/L/L", "L/L/H", "L/H/L", the jitter amplitude is for ILRCK and 1UI (Unit Interval) is one cycle of ILRCK. When FSI = 48kHz, 1UI is 1/48kHz = 20.8s. - When PLL2-0 = "H/*/*" (*: Don't care), the jitter amplitude is for IBICK and 1UI (Unit Interval) is one cycle of IBICK. When FSI = 48kHz, 1UI is 1/(64 x 48kHz) = 326ns. Figure 17. Jitter Tolerance
MS0288-E-01 - 21 -
2004/08
ASAHI KASEI
[AK4124]
PACKAGE
30pin VSOP (Unit: mm)
*9.70.1 0.3 30 1.5MAX
16 A 7.60.2 0.15 +0.10 -0.05 Detail A 0.450.2
1 0.220.1
15 0.65
0.12 M
1.20.10
0.08
NOTE: Dimension "*" does not include mold flash.
Material & Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
MS0288-E-01 - 22 -
0.10 -0.05
+0.10
5.60.1
2004/08
ASAHI KASEI
[AK4124]
MARKING
AKM AK4124VF XXXBYYYYC
XXXBYYYYC
Date code identifier
XXXB :Lot number (X : Digit number, B : Alpha character) YYYYC : Assembly date (Y : Digit number, C : Alpha character)
Revision History
Date (YY/MM/DD) 04/01/26 04/08/09 Revision 00 01 Reason First Edition Add Spec Add Spec Page 7 21 Contents Add FILTER CHARACTERISTICS Add Jitter Tolerance
MS0288-E-01 - 23 -
2004/08
ASAHI KASEI
[AK4124]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0288-E-01 - 24 -
2004/08

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